Patent Number: 7,821,519

Title: Scalable unified memory architecture

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Inventors: Perego; Richard E. (San Jose, CA)

Assignee: Rambus Inc.

International Classification: G06F 15/167 (20060101); G06F 13/14 (20060101); G06F 15/80 (20060101)

Expiration Date: 2018-10-26 0:00:00