Patent Number: 7,821,656

Title: Method of drawing images using a dynamic reconfigurable processor, circuit therefor and image output control apparatus

Abstract: A drawing processing circuit includes a plurality of rasterizing means capable of executing rasterizing processes in parallel. Each rasterizing means includes a dynamic reconfigurable processor. Data described by a page description language is received, analyzed, and converted into intermediate data for each drawn object. Before execution of a rasterizing process, scheduling data of reconfiguration of the processor is generated by estimating the process time of each rasterizing process on the basis of the intermediate data. The plurality of rasterizing means rasterize the data to bitmap data on the basis of the intermediate data while reconfiguring the processor on the basis of the generated scheduling data. In addition, the process time of each of the plurality of rasterizing means is determined on the basis of the scheduling data. The scheduling data is corrected so as to make the process times of the plurality of rasterizing means substantially equal. With this arrangement, a method of drawing image, which reduces the waste of hardware resources and perform a high-speed drawing process, a circuit thereof, and a print control apparatus are provided.

Inventors: Ito; Nobuyasu (Yokohama, JP), Tachikawa; Tomohiro (Kawasaki, JP)

Assignee: Canon Kabushiki Kaisha

International Classification: G06F 3/12 (20060101); G06F 9/46 (20060101)

Expiration Date: 2018-10-26 0:00:00