Patent Number: 7,821,734

Title: Head IC, read circuit and medium storage device

Abstract: A head IC adjusts an amplitude level of a read signal of a head to adjust dispersion of the output characteristic of the head and to adjust the read signal within the input dynamic range of the AGC of a read channel. An AGC amplifier is installed in a head IC connected to a read channel and a feedback response speed of an AGC circuit of the head IC is set to be sufficiently slower than a feedback response speed of an AGC circuit of the read channel. Also a peak hold circuit and an amplitude limiting circuit are installed in the head IC, and gain is adjusted with a holding value of the peak hold circuit. An initial gain can therefore be stably adjusted at high-speed without being influenced by signals having a small amplitude on the medium.

Inventors: Amemiya; Yoshihiro (Kawasaki, JP)

Assignee: Toshiba Storage Device Corporation

International Classification: G11B 5/02 (20060101)

Expiration Date: 2018-10-26 0:00:00