Patent Number: 7,821,804

Title: Semiconductor integrated circuit

Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

Inventors: Sekiguchi; Tomonori (Kokubunji, JP), Takemura; Riichiro (Tokyo, JP), Kajigaya; Kazuhiko (Iruma, JP), Kimura; Katsutaka (Akishima, JP), Takahashi; Tsugio (Hamura, JP)

Assignee: Elpida Memory, Inc.

International Classification: G11C 5/06 (20060101)

Expiration Date: 2018-10-26 0:00:00