Patent Number: 7,821,856

Title: Memory device having an evaluation circuit

Abstract: A memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of the bit line and the reference line. Inputs of the evaluation circuit are directly connected to the bit line. Outputs of the evaluation circuit are coupled to the bit line via a switch.

Inventors: Beer; Peter (Weilheim, DE)

Assignee: Qimoda AG

International Classification: G11C 7/00 (20060101); H03F 3/45 (20060101)

Expiration Date: 2018-10-26 0:00:00