Patent Number: 7,821,862

Title: Semiconductor memory circuit

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Inventors: Akiba; Takesada (Hachioji, JP), Ueda; Shigeki (Hachioji, JP), Tachibana; Toshikazu (Tachikawa, JP), Horiguchi; Masashi (Koganei, JP)

Assignee: Renesas Electronics Corporation

International Classification: G11C 5/14 (20060101); G11C 8/00 (20060101)

Expiration Date: 2018-10-26 0:00:00