Patent Number: 7,822,881

Title: Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)

Abstract: In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Inventors: Vorbach; Martin (D-76149 Karlsruhe, DE), Munch; Robert (D-76149 Karlsruhe, DE)

Assignee:

International Classification: G06F 3/00 (20060101); G06F 15/76 (20060101)

Expiration Date: 2018-10-26 0:00:00