Patent Number: 7,822,926

Title: Cache memory

Abstract: A data processor includes a cache memory having a plurality of cache rows each row storing a cache line of data values, a memory management unit responsive to a page table entry to control access to a corresponding group of memory addresses forming a memory page, and a cache controller coupled to said cache memory and responsive to a cache miss to trigger a line fill operation to store data values into a cache row. The cache controller is responsive to a cache line size specifier associated with at least one page table entry to vary the number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier. Controlling cache line size on a page basis is more efficient than controlling cache line size on a cache row or virtual address basis.

Inventors: Croxford; Daren (Burwell, GB), Aldworth; Peter James (Cambridge, GB)

Assignee: ARM Limited

International Classification: G06F 13/00 (20060101)

Expiration Date: 2018-10-26 0:00:00