Patent Number: 7,823,035

Title: System and methods of balancing scan chains and inserting the balanced-length scan chains into hierarchically designed integrated circuits

Abstract: A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L.

Inventors: Litten; David D. (Jericho, VT), Oakland; Steven F. (Colchester, VT)

Assignee: International Business Machines Corporation

International Classification: G01R 31/28 (20060101); G06F 17/50 (20060101)

Expiration Date: 2018-10-26 0:00:00