Patent Number: 7,823,050

Title: Low area architecture in BCH decoder

Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t-1)/(codeword_len-3).ltoreq.X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Inventors: Gasanov; Elyar E. (Moscow, RU), Andreev; Alexander (San Jose, CA), Neznanov; Ilya V. (Moscow, RU), Panteleev; Pavel A. (Moscow, RU), Gashkov; Sergei (Moscow, RU)

Assignee: LSICorporation

International Classification: H03M 13/00 (20060101)

Expiration Date: 2018-10-26 0:00:00