Patent Number: 7,823,097

Title: Unrolling hardware design generate statements in a source window debugger

Abstract: Unrolling the "generate" statement of a hardware description language ("HDL") and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.

Inventors: Drasny; Gabor (Poughkeepsie, NY), Bobok; Gabor (Schenectady, NY), El-Zein; Ali (Austin, TX), Zaraket; Fadi (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 2018-10-26 0:00:00