Patent Number: 7,823,098

Title: Method of designing a digital circuit by correlating different static timing analyzers

Abstract: A method of designing a digital circuit is described, so that it is likely to pass a signoff time test. The method begins with the running of a basic static time test on a partially developed version of the digital circuit, next a signoff time test is run for the partially developed version of the digital system. The differences between the results of the basic static time test and the signoff time test are noted and the prospective basic static time test passing conditions are altered so that if a similar system passes the basic static time test with the altered passing conditions it will be more likely to pass the signoff time test. Then, the partially developed version of the digital system is altered to yield a second partially developed version and the first static time test is run, with the altered passing conditions on the second partially developed version.

Inventors: Moon; Cho W. (San Diego, CA), Gupta; Puneet (Santa Clara, CA), Donehue; Paul J. (San Jose, CA), Kahng; Andrew B. (Del Mar, CA)

Assignee: Tela Innovations, Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 2018-10-26 0:00:00