Patent Number: 7,823,107

Title: Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design

Abstract: An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

Inventors: Arsovski; Igor (Williston, VT), Bueti; Serafino (Waterbury, VT), Iadanza; Joseph A. (Hinesburg, VT), Norman; Jason M. (Essex Junction, VT), Shah; Hemen R. (South Burlington, VT), Ventrone; Sebastian T. (South Burlington, VT)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101); H04L 7/00 (20060101)

Expiration Date: 2018-10-26 0:00:00