Patent Number: 7,823,108

Title: Chip having timing analysis of paths performed within the chip during the design process

Abstract: An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

Inventors: Curtin; James J. (Fishkill, NY), Cadigan, Jr.; Michael J. (Brewster, NY), Hughes; Edward J. (Archbald, PA), Mcllvain; Kevin M. (Cold Spring, NY), Neves; Jose L. (Poughkeepsie, NY), Raphy; Ray (Poughkeepsie, NY), Search; Douglas S. (Red Hook, NY)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101); G06F 9/44 (20060101)

Expiration Date: 2018-10-26 0:00:00