Patent Number: 7,823,115

Title: Method of generating wiring routes with matching delay in the presence of process variation

Abstract: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

Inventors: Habitz; Peter A. (Hinesburg, VT), Hathaway; David J. (Underhill, VT), Hayes; Jerry D. (Milton, VT), Polson; Anthony D. (Jericho, VT)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 2018-10-26 0:00:00