Patent Number: 7,823,151

Title: Method of ensuring the integrity of TLB entries after changing the translation mode of a virtualized operating system without requiring a flush of the TLB

Abstract: Systems and methods are disclosed to support partial physical addressing modes on a virtual machine. An example method disclosed herein identifies a change of a first translation mode to a second translation mode on a host hardware platform, the host hardware platform including a processor, the processor further including region registers; identifies an address as cacheable or non-cacheable; saves contents of the region registers for the first translation mode to processor memory; updates content of the region registers corresponding to the second translation mode; identifies a change of the second translation mode to the first translation mode; and populates the region registers with the contents of the saved region registers corresponding to the first translation mode.

Inventors: Seth; Rohit (Santa Clara, CA), Sharma; Arun (Union City, CA)

Assignee: Intel Corporation

International Classification: G06F 9/455 (20060101); G06F 9/46 (20060101)

Expiration Date: 2018-10-26 0:00:00