Patent Number: 7,823,161

Title: Intelligent memory device with variable size task architecture

Abstract: A variable task size architecture is disclosed. A system partition is included that is dedicated to system use. The system partition contains a number of specifiers that describe the number of tasks in the system memory, and for each task partition, the location and size of a task status register, the number, location and size of each of a set of task data registers, and the size and starting location of task code. Specifiers include the word size in bytes, the number of words per increment, the number of increments per partition, the number of increments per data register, and the number of data registers. In one embodiment, the number of tasks is available from an input port. The task specifiers and the number of tasks are accessible to the scheduler unit via the data flow unit when a reset signal is released.

Inventors: Klingman; Edwin E. (San Gregorio, CA)


International Classification: G06F 9/54 (20060101); G06F 12/00 (20060101)

Expiration Date: 2018-10-26 0:00:00