Patent Number: 7,824,985

Title: Method for manufacturing a recessed gate transistor

Abstract: A method of manufacturing a recessed gate transistor includes forming a hard mask pattern over a substrate; and then forming a trench in the substrate by performing an etching process using the hard mask pattern as an etch mask; and then performing a pullback-etching process on the hard mask pattern to expose a source region in the substrate; and then forming a gate silicon layer in the trench and over the substrate including the hard mask pattern after performing the pullback-etching process; and then performing an etch-back process on the gate silicon layer to expose the hard mask pattern such that the uppermost surface of the gate silicon layer is below the uppermost surface of the hard mask pattern; and then removing the hard mask pattern; and then simultaneously etching the gate silicon layer and the exposed portion of the substrate.

Inventors: Lee; Kyu-Ok (Seongdong-gu, KR)

Assignee: Dongbu HiTek Co., Ltd.

International Classification: H01L 21/336 (20060101)

Expiration Date: 2019-11-02 0:00:00