Patent Number: 7,824,989

Title: Method for reducing overlap capacitance in field effect transistors

Abstract: A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.

Inventors: Zhu; Huilong (Poughkeepsie, NY), Gluschenkov; Oleg (Poughkeepsie, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/336 (20060101)

Expiration Date: 2019-11-02 0:00:00