Patent Number: 7,824,990

Title: Multi-metal-oxide high-K gate dielectrics

Abstract: A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.

Inventors: Chang; Vincent S. (Hsinchu, TW), Yen; Fong-Yu (Taoyuan County, TW), Lim; Peng-Soon (Hsinchu, TW), Ying; Jin (Singapore, SG), Tao; Hun-Jan (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

International Classification: H01L 21/336 (20060101); H01L 21/31 (20060101)

Expiration Date: 2019-11-02 0:00:00