Patent Number: 7,824,996

Title: Semiconductor device fabrication method and semiconductor device

Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.

Inventors: Hashimoto; Koji (Kanagawa-ken, JP), Inoue; Soichi (Kanagawa-ken, JP), Takahata; Kazuhiro (Kanagawa-ken, JP), Yoshikawa; Kei (Kanagawa-ken, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 21/302 (20060101)

Expiration Date: 2019-11-02 0:00:00