Patent Number: 7,825,019

Title: Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits

Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Inventors: Clevenger; Lawrence A. (LaGrangeville, NY), Grunow; Stephan (Poughkeepsie, NY), Kumar; Kaushik A. (Beacon, NY), Petrarca; Kevin Shawn (Newburgh, NY), Ramachandran; Vidhya (San Diego, CA)

Assignee: International Business Machines Corporation

International Classification: H01L 21/44 (20060101)

Expiration Date: 2019-11-02 0:00:00