Patent Number: 7,825,027

Title: Method for manufacturing memory device

Abstract: A method for manufacturing a memory device including a ferroelectric memory array region and a logic circuit region is provided. The method includes the steps of: forming, above a base substrate, a plurality of ferroelectric capacitors in the ferroelectric memory array region; forming a wiring layer above the base substrate in the logic circuit region; forming an interlayer dielectric layer that covers the ferroelectric capacitors and the wiring layer; etching the interlayer dielectric layer formed at least in the ferroelectric memory array region to form a concave section; polishing the interlayer dielectric layer by a CMP (chemical mechanical polishing) method; etching the interlayer dielectric layer above the ferroelectric capacitors and the wiring layer to form contact holes; and forming contact sections in the contact holes.

Inventors: Noda; Takafumi (Matsumoto, JP), Higuchi; Toshihiko (Kai, JP)

Assignee: Seiko Epson Corporation

International Classification: H01L 21/302 (20060101); H01L 21/461 (20060101)

Expiration Date: 2019-11-02 0:00:00