Patent Number: 7,825,450

Title: Sacrificial self-aligned interconnect structures

Abstract: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

Inventors: Walker; Michael A. (Boise, ID), Robinson; Karl M. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 27/108 (20060101); H01L 29/94 (20060101)

Expiration Date: 2019-11-02 0:00:00