Patent Number: 7,825,472

Title: Semiconductor device having a plurality of stacked transistors and method of fabricating the same

Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

Inventors: Park; Han-Byung (Seongnam-si, KR), Jung; Soon-Moon (Seongnam-si, KR), Lim; Hoon (Seoul, KR), Yeo; Cha-Dong (Suwon-si, KR), Son; Byoung-Keun (Suwon-si, KR), Shim; Jae-Joo (Suwon-si, KR), Hong; Chang-Min (Seoul, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 27/12 (20060101)

Expiration Date: 2019-11-02 0:00:00