Patent Number: 7,825,517

Title: Method for packaging semiconductor dies having through-silicon vias

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.

Inventors: Su; Chao-Yuan (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

International Classification: H01L 23/52 (20060101); H01L 23/48 (20060101); H01L 29/40 (20060101)

Expiration Date: 2019-11-02 0:00:00