Patent Number: 7,825,706

Title: Phase locked loop that sets gain automatically

Abstract: There is provided a phase locked loop, PLL, that sets gain automatically. The PLL comprises a frequency discriminator for providing a first signal that represents the difference between a first frequency and a second frequency. The PLL also comprises a comparator coupled to the frequency discriminator for receiving the first signal and providing a second signal based on information from the first signal. The second signal is representative of a gain setting for the phase locked loop to set.

Inventors: Smith; Alan Andrew (Farnborough, GB), Stuart, legal representative; Julie (Longfield, GB), Harris; Mark V. (Farnborough, GB)

Assignee: QUALCOMM Incorporated

International Classification: H03L 7/06 (20060101)

Expiration Date: 2019-11-02 0:00:00