Patent Number: 7,825,710

Title: Delay-locked loop circuits and method for generating transmission core clock signals

Abstract: A delay-locked loop (DLL) circuit and a method for generating transmission core clock signals are provided, where the DLL circuit receives an applied external clock signal and generates a transmission core clock signal, the DLL circuit includes a delay circuit unit and a transmission core clock signal generating unit, the delay circuit unit delays the external clock signal through a plurality of delay units configured in a chain type and outputs a plurality of reference clock signals having different phases, the transmission core clock signal generating unit independently selects and controls two reference signals from the plurality of reference clock signals and thus independently generates transmission core clock signals by the number corresponding to 1/2 times the number of reference clock signals, and the transmission core clock signals have different phases and a period equal to a period of the external clock signal, wherein transmission core clock signals having a precise phase difference are generated individually and independently.

Inventors: Kim; Nam-Seog (Suwon-si, KR), Cho; Uk-Rae (Suwon-si, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H03L 7/06 (20060101)

Expiration Date: 2019-11-02 0:00:00