Patent Number: 7,825,737

Title: Apparatus for low-jitter frequency and phase locked loop and associated methods

Abstract: A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

Inventors: Fang; Steve (Sunnyvale, CA), Cheng; Chi Fung (San Jose, CA)

Assignee: Marvell International Ltd.

International Classification: H03L 7/087 (20060101)

Expiration Date: 2019-11-02 0:00:00