Patent Number: 7,826,497

Title: Data receiving circuit that can correctly receive data, even when high-speed data transmission is performed, using small amplitude clock

Abstract: A data receiving circuit has a data input terminal, a conversion circuit converting an input signal received via the data input terminal, and a decision circuit making a decision on an output of the conversion circuit. The conversion circuit has a demultiplexer converting the input signal into a signal of a lower frequency than the frequency thereof at the data input terminal, and an output of the demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source.

Inventors: Doi; Yoshiyasu (Kawasaki, JP), Tamura; Hirotaka (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: H04J 3/04 (20060101); H03H 11/26 (20060101)

Expiration Date: 2019-11-02 0:00:00