Patent Number: 7,826,581

Title: Linearized digital phase-locked loop method for maintaining end of packet time linearity

Abstract: An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.

Inventors: Prather; Stephen M. (Austin, TX), Berzins; Matthew S. (Austin, TX), Cornell; Charles A. (Austin, TX), Larky; Steven P. (Del Mar, CA), Cetin; Joseph A. (San Diego, CA)

Assignee: Cypress Semiconductor Corporation

International Classification: H03D 3/24 (20060101)

Expiration Date: 2019-11-02 0:00:00