Patent Number: 7,827,386

Title: Controlling memory access devices in a data driven architecture mesh array

Abstract: A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.

Inventors: Lippincott; Louis A. (Chandler, AZ), Cheah; Chin Hong (Chandler, AZ)

Assignee: Intel Corporation

International Classification: G06F 15/00 (20060101); G06F 15/76 (20060101)

Expiration Date: 2019-11-02 0:00:00