Patent Number: 7,827,428

Title: System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture

Abstract: A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

Inventors: Arimilli; Lakshminarayana B. (Austin, TX), Arimilli; Ravi K. (Austin, TX), Drerup; Bernard C. (Austin, TX), Joyner; Jody B. (Austin, TX), Lewis; Jerry D. (Round Rock, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 1/00 (20060101); G06F 1/04 (20060101); G06F 1/12 (20060101)

Expiration Date: 2019-11-02 0:00:00