Patent Number: 7,827,433

Title: Time-multiplexed routing for reducing pipelining registers

Abstract: Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus registers placed at the ends of the bus wires can register or buffer the data signals transmitted over the bus wires. The registered signals may be passed on to deserializing circuitry for demultiplexing the data signals to provide parallel device input signals. The bus registers and the serializing/deserializing circuitry can be provided along signal paths that require additional latency.

Inventors: Hutton; Michael D. (Mountain View, CA)

Assignee: Altera Corporation

International Classification: G06F 5/06 (20060101)

Expiration Date: 2019-11-02 0:00:00