Patent Number: 7,827,461

Title: Low-density parity-check decoder apparatus

Abstract: A low-density parity-check (LDPC) decoder includes a plurality of bit node processing elements, and a plurality of check node processing elements. The LDPC decoder also includes a plurality of message passing memory blocks. A first routing matrix couples the plurality of bit node processing elements to the plurality of message passing memory blocks. A second routing matrix couples the plurality of check node processing elements to the plurality of message passing memory blocks. The first routing matrix and the second routing matrix enable each bit node to exchange LDPC decoding messages with an appropriate check node via a corresponding one of the message passing memory blocks.

Inventors: Low; Seo-How (San Jose, CA), Varnica; Nedeljko (Sunnyvale, CA), Burd; Gregory (San Jose, CA), Wu; Zining (Los Altos, CA)

Assignee: Marvell International Ltd.

International Classification: H03M 13/00 (20060101)

Expiration Date: 2019-11-02 0:00:00