Patent Number:
7,827,463
Title:
Semiconductor memory device
Abstract:
In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
Inventors:
Otsuka; Shuzo (Kawasaki, JP), Kawabata; Kuninori (Kawasaki, JP), Nakamura; Toshikazu (Kawasaki, JP), Kikutake; Akira (Kawasaki, JP)
Assignee:
Fujitsu Semiconductor Limited
International Classification:
H03M 13/00 (20060101)
Expiration Date:
2019-11-02 0:00:00