Patent Number: 7,955,921

Title: Full silicide gate for CMOS

Abstract: A method is provided for fabricating an n-type field effect transistor ("NFET") and a p-type field effect transistor ("PFET") in which the NFET and PFET are formed after which a protective hard mask layer, e.g., a dielectric stressor layer is formed to overlie edges of gates, source regions and drain regions of the PFET and NFET. Sputter etching can be used to remove a portion of the protective hard mask layer to expose the gates of the PFET and NFET. The semiconductor elements can be etched selectively with respect to the protective hard mask layer to reduce a thickness of the semiconductor elements. A metal may then be deposited and caused to react with the reduced thickness semiconductor element to form silicide elements of the gates.

Inventors: Zhu; Huilong (Poughkeepsie, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/8238 (20060101)

Expiration Date: 2019-06-07 0:00:00