Patent Number: 8,067,274

Title: Method of forming wiring on a plurality of semiconductor devices from a single metal plate, and a semiconductor construction assembly formed by the method

Abstract: In this manufacturing method of a semiconductor device, a metal plate having a plurality of projection electrodes in each of a plurality of semiconductor device formation areas is prepared. Next, the projection electrodes of each of the semiconductor formation areas are aligned corresponding to external connection electrodes of each semiconductor construction, and each semiconductor construction is separately arranged on the projection electrodes in the semiconductor device formation areas. Next, an insulating layer formation sheet is arranged on the metal plate, and the metal plate and the insulating layer formation sheet are joined by heat pressing. Then, the metal plate is patterned and a plurality of upper layer wirings that connect to the projection electrodes is formed.

Inventors: Mihara; Ichiro (Tachikawa, JP), Wakabayashi; Takeshi (Sayama, JP)

Assignee: Casio Computer Co., Ltd.

International Classification: H01L 21/00 (20060101)

Expiration Date: 2020-11-29 0:00:00