Patent Number: 8,089,295

Title: Wafer level balanced capacitance design for magnetic heads

Abstract: Embodiments of the invention provide methods, systems and apparatus for testing electronic components, and more specifically for testing magnetoresistive heads. A pair of top shield pads and a pair of bottom shield pads may be formed in a kerf region of a wafer on which magnetoresistive heads are formed. The top shield pads, bottom shield pads, and a magnetoresistive head may form a circuit that may be coupled with a testing circuit to exchange test signals configured to test the magnetic head. The pair of bottom shield pads may provide balanced impedance to substrate that nullifies the effects of broadband noise.

Inventors: Marley; Arley Cleveland (San Jose, CA), Seagle; David John (Morgan Hill, CA)

Assignee: Hitachi Global Storage Technologies Netherlands B.V.

International Classification: G01R 31/02 (20060101); G11B 5/127 (20060101)

Expiration Date: 2020-01-03 0:00:00