Patent Number: 8,089,304

Title: Clock frequency division methods and circuits

Abstract: Frequency division methods and circuits are provided for producing an output clock signal with a frequency related to the frequency of an input clock signal by a predetermined factor. The method and circuit rely on the input clock signal and on feedback from the output signal to produce an intermediate signal. The frequency of the intermediate signal is divided to produce the output clock signal. The method and circuit may be implemented using few circuit components. In an exemplary embodiment, the method and circuit may be used to produce an output clock signal with a frequency that is two-and-a-half times lower than the frequency of the input clock signal.

Inventors: Jamal; Shafiq M. (Gilroy, CA)

Assignee: Marvell International Ltd.

International Classification: H03B 19/00 (20060101)

Expiration Date: 2020-01-03 0:00:00