Patent Number: 8,089,486

Title: Tiled prefetched and cached depth buffer

Abstract: A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Inventors: Anderson; Michael Hugh (Leucadia, CA), Chuang; Dan Minglun (San Diego, CA), Shippee; Geoffrey (Palo Alto, CA), Dhawan; Rajat Rajinderkumar (San Diego, CA), Yu; Chun (San Diego, CA)

Assignee: QUALCOMM Incorporated

International Classification: G06T 1/20 (20060101)

Expiration Date: 2020-01-03 0:00:00