Patent Number: 8,219,745

Title: Memory controller to utilize DRAM write buffers

Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Inventors: Bellows; Mark David (Rochester, MN), Haselhorst; Kent Harold (Byron, MN), Heakendorf; Ryan Abel (Rochester, MN), Ganfield; Paul Allen (Rochester, MN), Ozguner; Tolga (Rochester, MN)

Assignee: International Business Machines Corporation

International Classification: G06F 12/00 (20060101)

Expiration Date: 2020-07-10 0:00:00