Patent Number: 8,219,757

Title: Apparatus and method for low touch cache management

Abstract: In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.

Inventors: Hinton; Glenn (Portland, OR), Juenemann; Dale (North Plains, OR), Tetrick; R. Scott (Portland, OR)

Assignee: Intel Corporation

International Classification: G06F 12/00 (20060101)

Expiration Date: 2020-07-10 0:00:00