Patent Number: 8,298,875

Title: Method for fabrication of a semiconductor device and structure

Abstract: A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.

Inventors: Or-Bach; Zvi (San Jose, CA), Sekar; Deepak C. (San Jose, CA), Cronquist; Brian (San Jose, CA), Lim; Paul (San Jose, CA)

Assignee: Monolithic 3D Inc.

International Classification: H01L 21/20 (20060101)

Expiration Date: 2020-10-30 0:00:00