Patent Number: 8,492,221

Title: Method for fabricating power semiconductor device with super junction structure

Abstract: A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.

Inventors: Lin; Yung-Fa (Hsinchu, TW), Hsu; Shou-Yi (Hsinchu County, TW), Wu; Meng-Wei (Hsinchu, TW), Chang; Chia-Hao (Hsinchu, TW)

Assignee: Anpec Electronics Corporation

International Classification: H01L 21/8242 (20060101)

Expiration Date: 2021-07-23 0:00:00