Patent Number: 8,492,289

Title: Barrier layer formation for metal interconnects through enhanced impurity diffusion

Abstract: A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.

Inventors: Edelstein; Daniel C. (White Plains, NY), Nogami; Takeshi (Schenectady, NY), Shobha; Hosadurga K. (Niskayuna, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/31 (20060101)

Expiration Date: 2021-07-23 0:00:00