Patent Number: 8,502,581

Title: Multi-phase digital phase-locked loop device for pixel clock reconstruction

Abstract: A reconstruction circuit for the pixel clock in digital display units receiving analog display data uses a multi-phase reference clock and an all digital PLL for clock generation and synchronization to an external sync signal. A phase/frequency detector in the digital PLL uses a multi-phase reference clock to achieve a high resolution of the phase error. The digital PLL control algorithm can be implemented with a single loop and can achieved arbitrary large, externally controlled, phase difference between the generated pixel clock and the input sync signal.

Inventors: Opris; Ion E. (San Jose, CA)


International Classification: H03L 7/06 (20060101)

Expiration Date: 2021-08-06 0:00:00