Patent Number: 8,575,613

Title: Implementing vertical signal repeater transistors utilizing wire vias as gate nodes

Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

Inventors: Erickson; Karl R. (Rochester, MN), Paone; Phil C. (Rochester, MN), Paulsen; David P. (Dodge Center, MN), Sheets, II; John E. (Zumbrota, MN), Uhlmann; Gregory J. (Rochester, MN), Williams; Kelly L. (Rochester, MN)

Assignee: International Business Machines Corporation

International Classification: H01L 29/10 (20060101)

Expiration Date: 1/05/12017