Patent Number: 8,575,624

Title: Semiconductor device

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Inventors: Kanemura; Takahisa (Yokohama, JP), Kondo; Masaki (Kawasaki, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 29/15 (20060101)

Expiration Date: 1/05/12017