Patent Number: 8,575,652

Title: Semiconductor device and manufacturing method thereof

Abstract: An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.

Inventors: Kamata; Yoshiki (Tokyo, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101)

Expiration Date: 1/05/12017